With the continued miniaturization of integrated circuit (IC) devices, the current trend is to produce integrated circuits having shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation (STI) structures, and self-aligned silicide (salicide) processes, all of which are used in advanced sub-quarter-micron complementary metal oxide semiconductor (CMOS) technologies. All of these processes cause the related CMOS IC products to become more susceptible to damage due to ESD events. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits on the IC from ESD damage. ESD protection circuits are typically provided for input/output (“I/O”) pads. However, conventional ESD protection circuits cause undesirable signal losses.